Performance Estimation of Embedded Software with Pipeline and Cache Hazard Modeling

A major challenge in telecommunication design is introducing flexibility while still meeting real-time performance goals. Keeping both flexibility and performance while minimizing cost, leads to mixed hardware-software systems. In the absence of a generic partitioning algorithm, accurate cost and performance modeling become crucial when exploring architectural alternatives. This paper presents a case study in which we apply an efficient software performance estimation method to an ATM (Asynchronous Transfer Mode) network application. Since the execution efficiency of pipelined RISC machines heavily depends on the characteristics of the application and the underlying memory hierarchy, effects from pipelineand cache stalls must be taken into account. The aim of our methodology is to increase the predictability of software execution time in order to minimize expensive hardware implementation. Key-words: Software estimation, RISC, Cache, ATM, Co-desing